This invention relates to a speech processing device, more particularly to speech analysis and synthesis, used in sub-band speech analyzing and synthesizing apparatus.
The prior art of this technology is represented by the sub-band speech analyzing and synthesizing system described on pages 1069 to 1085 of The Bell System Technical Journal, 55[8] (1976-10), which will be referred to as the SBC (sub-band coding) system. As indicated in FIG. 1, the SBC system divides the speech signal into a number of frequency bands (usually four to eight) called channels, and codes and decodes the output of each channel separately. FIG. 2 shows the basic circuit configuration of the SBC system. The operation of this circuit is depicted in FIGS. 3A to 3E.
The operation of the SBC system will be explained next with reference to FIG. 2 and FIGS. 3A to 3E.
First, the analyzing device in the SBC system operates as follows.
An analog speech signal input from a microphone (not shown) is fed through a low-pass filter (not shown) which removes frequencies higher than half the rate at which the signal will be sampled, then to an A/D converter (not shown) which converts the analog signal to a digital signal S(n) by sampling it at this sampling rate. The letter n denotes the sample number. The digitized input signal S(n) is fed to a bandpass filter 201 which extracts a particular (k+h) band (W.sub.1k to W.sub.2k). The output from this bandpass filter 201 is next cosine-modulated by multiplication in a multiplier 202 by a cosine wave having the frequency W.sub.1k indicated in FIG. 3B, and is thereby shifted into the baseband (0-W.sub.k) as shown in FIG. 3C. Unwanted frequency components above 2W.sub.1k which arises at this point (for example, the components indicated by dashed lines in FIG. 3C) are removed by a low-pass filter 203. The resulting signal r.sub.k (n) requires only frequency components equal to or less than W.sub.k, so necessary and sufficient information can be preserved by sampling it at a rate of 2W.sub.k. A decimator 204 therefore decimates (performs sampling rate reduction on) the unnecessarily high sampling rate to 2W.sub.k. The decimated signal is encoded by the coder 205 and the coded signal is sent to the synthesizing device.
To reconstruct the full-band signal, the synthesizing device performs exactly the reverse of the process performed by the analyzing device. Specifically, the coded signal is decoded by the decoder 206, then the interpolator 207 restores the decimated signal to its original sampling rate by interpolation. The signal output from the interpolator 207 is sent to a multiplier 208 and modulated by multiplication by a cosine wave with a frequency of W.sub.1k, as shown in FIG. 3D. Then the signal is shifted from the baseband (0-W.sub.k) back to its original frequency band (W.sub.1k to W.sub.2k) as in FIG. 3E, and components outside this band (w.sub.1k to W.sub.2k) are removed by a bandpass filter 209.
The result is that the synthesizing device outputs the signal S.sub.k (n).
The process described above is performed for each channel. Finally, the outputs in all channels are added to obtain the output signal.
Although the SBC system basically operates as described above, the circuit in FIG. 2 is not usually implemented directly. Instead, to reduce the amount of circuitry, a circuit configuration without bandpass filters, like that in FIG. 4 has been proposed for the SBC system.
The operation of the circuit in FIG. 4 will be explained next.
First the analysing device complex-modulates the digitized input signal S(n) by means of the complex signal e.sup.j.omega. k.sup.n (where .omega..sub.k =(W.sub.1k +W.sub.2k)/2). This complex modulation is accomplished by performing cosine modulation (using the modulating signal cos.omega..sub.k n) in a multiplier 301 and sine modulation (using the modulating signal sin.omega..sub.k n) in a multiplier 302. The outputs from the multipliers 301 and 302 are filtered by low-pass filters 303 and 304 with a bandwidth 0-W.sub.k/2.
The real part a.sub.k (n) of the complex signal a.sub.k (n)+jb.sub.k (n) is output from the low-pass filter 303, and the imaginary part b.sub.k (n) output from the low-pass filter 304. The signals a.sub.k (n) and b.sub.k (n) are decimated to the frequency W.sub.k by decimators 305 and 306, respectively, then encoded by a coder 307 and sent to the synthesizing device.
In the synthesizing device, the encoded signals are decoded by a decoder 308, restored to their original sampling rates by the interpolators 309 and 310, filtered by low-pass filters 311 and 312 with a bandwidth 0-W.sub.k/2, then demodulated by a multiplier 313 which performs cosine modulation and a multiplier 314 which performs sine modulation. An adder 315 adds the resulting cosine and sine components to generate the signal for the particular channel.
The process described above is performed for each channel. Finally, the outputs in all channels are added to obtain the output signal.
Although smaller than the circuit shown in FIG. 1 due to the elimination of the first-stage bandpass filters, the circuit configuration of the prior art as shown in FIG. 4 is far from providing a practical speech processing device, because a low-pass filter is still required in each channel. Another drawback of the speech processing devices in the prior art is that two computational processes, one for modulation and one for filtering, are necessary, so if fixed-point arithmetic is used, the accumulation of computational errors in the two processes raises problems.